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ds2252t secure microcontroller module ds2252t 021998 1/15 features ? 8051 compatible microcontroller for secure/sensitive applications 32k, 64k, or 128k bytes of nonvolatile sram for program and/or data storage insystem programming via onchip serial port capable of modifying its own program or data memory in the end system ? firmware security features: memory stored in encrypted form encryption using onchip 64bit key automatic true random key generator sdi self destruct input improved security over previous generations protects memory contents from piracy ? crashproof operation maintains all nonvolatile resources for over 10 years in the absence of power powerfail reset early warning powerfail interrupt watchdog timer precision reference for power monitor ? fully 8051 compatible 128 bytes scratchpad ram two timer/counters onchip serial port 32 parallel i/o port pins ? permanently powered real time clock package outline 40pin simm 1202140 description the ds2252t is an 8051 compatible microcontroller based on nonvolatile ram technology. it is designed for systems that need to protect memory contents from dis- closure. this includes key data, sensitive algorithms, and proprietary information of all types. like other mem- bers of the secure microcontroller family, it provides full compatibility with the 8051 instruction set, timers, serial port, and parallel i/o ports. by using nv ram instead of rom, the user can program, then reprogram the micro- controller while insystem. this allows frequent chang- ing of sensitive processes with minimal effort. the ds2252t provides an array of mechanisms to prevent an attacker from examining the memory. it is designed to resist all levels of threat including observation, analy- sis, and physical attack. as a result, a massive effort would be required to obtain any information about memory contents. furthermore, the asofto nature of the ds2252t allows frequent modification of secure information. this minimizes that value of any informa- tion that is obtained.
ds2252t 021998 2/15 using a security system based on the ds5002fp, the ds2252t protects the memory contents from disclo- sure. it loads program memory via its serial port and encrypts it in realtime prior to storing it in sram. once encrypted, the ram contents and the program flow are unintelligible. the real data exists only inside the pro- cessor chip after being decrypted. any attempt to dis- cover the onchip data, encryption keys, etc., results in its destruction. extensive use of nonvolatile lithium backed technology create a microcontroller that retains data for over 10 years at room temperature, but which can be erased instantly if tampered with. the ds2252t even interfaces directly to external tamper protection hardware. the ds2252t provides a permanently powered real time lock with interrupts for time stamp and date. it keeps time to one hundredth of a second using its on board 32 khz crystal. like other secure microcontrollers in the family, the ds2252t provides crashproof operation in portable systems or systems with unreliable power. these fea- tures include the ability to save the operating state, powerfail reset, powerfail interrupt, and watchdog timer. all nonvolatile memory and resources are main- tained for over 10 years at room temperature in the absence of power. a user loads programs into the ds2252t via its onchip serial bootstrap loader. this function supervises the loading of software into nv ram, validates it, then becomes transparent to the user. it also manages the loading of new encryption keys automatically. software is stored in onboard cmos sram. using its internal partitioning, the ds2252t can divide a common ram into user selectable program and data segments. this partition can be selected at program loading time, but can be modified anytime later. the microcontroller will decode memory access to the sram, access memory via its bytewide bus and writeprotect the memory por- tion designated as program (rom). a detailed summary of the security features is provided in the user's guide section of the secure microcontrol- ler data book. an overview is also available in the ds5002fp data sheet. ordering information part number ram size max crystal speed timekeeping? ds2252t3216 32k bytes 16 mhz yes ds2252t6416 64k bytes 16 mhz yes ds2252t12816 128k bytes 16 mhz yes operating information is contained in the user's guide section of the secure microcontroller data book. this data sheet provides ordering information, pinout, and electrical specifications.
ds2252t 021998 3/15 ds2252t block diagram figure 1 ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? p0.00.7 p1.01.7 p2.02.7 p3.03.7 rst ale xtal1 xtal2 gnd prog sdi v cc ds5002fp ??????? ??????? ??????? ??????? ??????? ??????? ??????? ??????? ??????? ??????? ??????? ??????? ??????? ??????? ??????? ??????? ??????? ??????? ??????? ??????? v cco ce1 r/w ce2 bytewide data bus bytewide address bus +3v 32k or 128k sram ds1283 real time clock ds2252t 32k sram (64 only) pe1 p3.2 intp
ds2252t 021998 4/15 pin assignment 1 p1.0 11 p1.5 21 p3.1 txd 31 p3.6 wr 2v cc 12 p0.4 22 ale 32 p2.4 3 p1.1 13 p1.6 23 p3.2 int0 33 p3.7 rd 4 p0.0 14 p0.5 24 prog 34 p2.3 5 p1.2 15 p1.7 25 p3.3 int1 35 xtal2 6 p0.1 16 p0.6 26 p2.7 36 p2.2 7 p1.3 17 rst 27 p3.4 t0 37 xtal1 8 p0.2 18 p0.7 28 p2.6 38 p2.1 9 p1.4 19 p3.0 rxd 29 p3.5 t1 39 gnd 10 p0.3 20 sdi 30 p2.5 40 p2.0 pin description pin description 4, 6, 8, 10, 12, 14, 16, 18 p0.0 p0.7. general purpose i/o port 0. this port is opendrain and can not drive a logic 1. it requires external pullups. port 0 is also the multiplexed expanded address/data bus. when used in this mode, it does not require pullups. 1, 3, 5, 7, 9, 11, 13, 15 p1.0 p1.7. general purpose i/o port 1. 40, 38, 36, 34, 32, 30, 28, 26 p2.0 p2.7. general purpose i/o port 2. also serves as the msb of the expanded address bus. 19 p3.0 rxd. general purpose i/o port pin 3.0. also serves as the receive signal for the on board uart. this pin should not be connected directly to a pc com port. 21 p3.1 txd. general purpose i/o port pin 3.1. also serves as the transmit signal for the on board uart. this pin should not be connected directly to a pc com port. 23 p3.2 int0 . general purpose i/o port pin 3.2. also serves as the active low external interrupt 0. this pin is also connected to the intp output of the ds1283 real time clock. 25 p3.3 int1 . general purpose i/o port pin 3.3. also serves as the active low external interrupt 1. 27 p3.4 t0. general purpose i/o port pin 3.4. also serves as the timer 0 input. 29 p3.5 t1. general purpose i/o port pin 3.5. also serves as the timer 1 input. 31 p3.6 wr . general purpose i/o port pin. also serves as the write strobe for expanded bus opera- tion. 33 p3.7 rd . general purpose i/o port pin. also serves as the read strobe for expanded bus opera- tion. 17 rst active high reset input. a logic 1 applied to this pin will activate a reset state. this pin is pulled down internally, can be left unconnected if not used. an rc poweron reset circuit is not needed and is not recommended. 22 ale address latch enable. used to demultiplex the multiplexed expanded address/data bus on port 0. this pin is normally connected to the clock input on a '373 type transparent latch.
ds2252t 021998 5/15 pin description 35, 37 xtal2, xtal1. used to connect an external crystal to the internal oscillator. xtal1 is the input to an inverting amplifier and xtal2 is the output. 39 gnd logic ground. 2 v cc +5v . 24 prog invokes the bootstrap loader on a falling edge. this signal should be debounced so that only one edge is detected. if connected to ground, the microcontroller will enter bootstrap loading on power up. this signal is pulled up internally. 20 sdi self destruct input. a logic 1 applied to this input causes a hardware unlock. this involves the destruction of encryption keys, vector ram, and the momentary removal of power from v cco . this pin should be grounded if not used. instruction set the ds2252t executes an instruction set that is object code compatible with the industry standard 8051 micro- controller. as a result, software development packages such as assemblers and compilers that have been writ- ten for the 8051 are compatible with the ds2252t. a complete description of the instruction set and operation are provided in the user's guide section of the secure microcontroller data book. memory organization figure 2 illustrates the memory map accessed by the ds2252t. the entire 64k of program and 64k of data are available to the bytewide bus. this preserves the i/o ports for application use. an alternate configuration allows dynamic partitioning of a 64k space as shown in figure 3. any data area not mapped into the nv ram is reached via the expanded bus on ports 0 and 2. off board program memory is not available for security rea- sons. selecting pes=1 provides access to the real time clock as shown in figure 4. these selections are made using special function registers. the memory map and its controls are covered in detail in the user's guide section of the secure microcontroller data book.
ds2252t 021998 6/15 ds2252t memory map in nonpartitionable mode (pm=1) figure 2 data memory (movx) 64k nv ram data program memory nv ram program ffffh 0000h ds2252t memory map in partitionable mode (pm=0) figure 3 ????? ????? ????? ????? ????? ????? ????? ????? ????? ffffh 0000h = nv ram memory legend: nv ram data nv ram program partition = ?? ?? = program memory expanded bus (ports 0 and 2) not available data memory (movx) note: partitionable mode is not supported on the 128kb version of the ds2252t.
ds2252t 021998 7/15 ds2252t memory map with (pes=1) figure 4 ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? data memory (movx) 64k 16k realtime clock ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? program memory nv ram program ffffh c000h 8000h 4000h 0000h partition ?? ?? not accessible power management the ds2252t monitors v cc to provide powerfail reset, early warning powerfail interrupt, and switch over to lithium backup. it uses an internal bandgap ref- erence in determining the switch points. these are called v pfw , v ccmin , and v li respectively. when v cc drops below v pfw , the ds2252t will perform an inter- rupt vector to location 2bh if the powerfail warning was enabled. full processor operation continues regard- less. when power falls further to v ccmin , the ds2252t invokes a reset state. no further code execution will be performed unless power rises back above v ccmin . all decoded chip enables and the r/w signal go to an inac- tive (logic 1) state. v cc is still the power source at this time. when v cc drops further to below v li , internal cir- cuitry will switch to the builtin lithium cell for power. the majority of internal circuits will be disabled and the remaining nonvolatile states will be retained. the user's guide has more information on this topic. the trip points v ccmin and v pfw are listed in the electrical spec- ifications.
ds2252t 021998 8/15 absolute maximum ratings* voltage on any pin relative to ground 0.3v to +7.0v operating temperature 0 c to 70 c storage temperature 40 c to +70 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc characteristics (t a =0 c to 70 c; v cc =5v 10%) parameter symbol min typ max units notes input low voltage v il 0.3 +0.8 v 1 input high voltage v ih1 2.0 v cc +0.3 v 1 input high voltage (rst, xtal1, prog ) v ih2 3.5 v cc +0.3 v 1 output low voltage @ i ol =1.6 ma (ports 1, 2, 3) v ol1 0.15 0.45 v 1 output low voltage @ i ol =3.2 ma (ports 0, ale) v ol2 0.15 0.45 v 1 output high voltage @ i oh =80 m a (ports 1, 2, 3) v oh1 2.4 4.8 v 1 output high voltage @ i oh =400 m a (ports 0, ale) v oh2 2.4 4.8 v 1 input low current v in =0.45v (ports 1, 2, 3) i il 50 m a transition current; 1 to 0 v in =2.0v (ports 1, 2, 3) i tl 500 m a input leakage current 0.45 ds2252t 021998 9/15 ac characteristics (t a = 0 c to70 c; v cc =0v to 5v) parameter symbol min typ max units notes sdi pulse reject (4.5v ds2252t 021998 10/15 expanded data memory read cycle 27 19 21 14 16 26 4 3 22 20 17 18 ale port 0 port 2 p2.7p2.0 or a15a8 from dph a15a8 from pch data in instr in a7a0 (pcl) a7a0 (rn or dpl) rd 2 expanded data memory write cycle 27 21 15 23 3 4 24 25 22 ale port 0 port 2 wr data out a7a0 (rn or dpl) a7a0 (pcl) instr in p2.7p2.0 or a15a8 from dph a15a8 from pch
ds2252t 021998 11/15 ac characteristics (cont'd) external clock drive (t a = 0 c to70 c; v cc = 5v + 10%) # parameter symbol min max units 28 external clock high time @12 mhz @16 mhz t clkhpw 20 15 ns ns 29 external clock low time @12 mhz @16 mhz t clklpw 20 15 ns ns 30 external clock rise time @12 mhz @16 mhz t clkr 20 15 ns ns 31 external clock fall time @12 mhz @16 mhz t clkf 20 15 ns ns external clock timing 28 29 30 31 1 ac characteristics (cont'd) power cycling timing (t a = 0 c to70 c; v cc = 5v + 10%) # parameter symbol min max units 32 slew rate from v ccmin to 3.3v t f 130 m s 33 crystal startup time t csu (note 8) 34 poweron reset delay t por 21504 t clk
ds2252t 021998 12/15 power cycle timing v cc v pfw v ccmin v li interrupt service routine clock osc internal reset lithium current 32 33 34 ac characteristics (cont'd) serial port timing mode 0 (t a = 0 c to70 c; v cc = 5v + 10%) # parameter symbol min max units 35 serial port clock cycle time t spclk 12t clk m s 36 output data setup to rising clock edge t doch 10t clk 133 ns 37 output data hold after rising clock edge t chdo 2t clk 117 ns 38 clock rising edge to input data valid t chdv 10t clk 133 ns 39 input data hold after rising clock edge t chdiv 0 ns
ds2252t 021998 13/15 serial port timing mode 0 instruction 012345678 ale clock data out input data 01234567 35 37 36 39 38 set ti set ri valid valid valid valid valid valid valid clear ri write to sbuf register notes: 1. all voltage referenced to ground. 2. sdi should be taken to a logic high when v cc =+5v, and to approximately 3v when v cc <3v. 3. sdi is deglitched to prevent accidental destruction. the pulse must be longer than t spr to pass the deglitcher, but sdi is not guaranteed unless it is longer than t spa . 4. maximum operating i cc is measured with all output pins disconnected; xtal1 driven with t clkr , t clkf =10 ns, v il = 0.5v; xtal2 disconnected; rst = port0 = v cc . 5. idle mode i idle is measured with all output pins disconnected; xtal1 driven with t clkr , t clkf = 10 ns, v il = 0.5v; xtal2 disconnected; port0 = v cc , rst = v ss . 6. stop mode i stop is measured with all output pins disconnected; port0 = v cc ; xtal2 not connected; rst = xtal1 = v ss . 7. pin capacitance is measured with a test frequency 1 mhz, t a = 25 c. 8. crystal startup time is the time required to get the mass of the crystal into vibrational motion from the time that power is first applied to the circuit until the first clock pulse is produced by the onchip oscillator. the user should check with the crystal vendor for a worst case specification on this time.
f (side a) (side b) a c g c l d e i i k l h m j o n p (side b) u1b u1a u3 u2 ds2252t 021998 14/15 package drawing pkg inches dim min max a 2.645 2.655 b 2.379 2.389 c 0.995 1.005 d 0.395 0.405 e 0.245 0.255 f 0.050 bsc g 0.075 0.085 h 0.245 0.255 i 0.950 bsc j 0.120 0.130 k 1.320 1.330 l 1.445 1.455 m 0.057 0.067 n 0.300 o 0.165 p 0.047 0.054
ds2252t 021998 15/15 data sheet revision summary the following represent the key differences between 12/13/95 and 08/16/96 version of the ds2252t data sheet. please review this summary carefully. 1. change v cc slew rate specification to reference 3.3v instead of v li . 2. add minimum value to pcb thickness. the following represent the key differences between 08/16/96 and 05/28/97 version of the ds2252t data sheet. please review this summary carefully. 1. ac characteristics for batterybacked sdi pulse specification added.

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